1. Field of the Invention
The present invention relates to image display controlling devices, and in particular, to an image display controlling device for displaying an image on a display unit for monitoring an imaging condition of a photographic subject in a camera module. The camera module is a digital still camera or a digital video camera, and the display unit is a view finder or an LCD (liquid crystal display) monitor.
2. Description of the Background Art
In a camera using a solid-state imaging device such as a digital still camera and digital video camera, a view finder using a liquid crystal display (LCD) or an LCD monitor is used for visually checking a subject to be imaged or picked up. In displaying an image on a view finder of a digital still camera, image data is processed in the following manner as disclosed in Japanese Patent Laying-Open No. 2006-267381 (Patent Document 1). Specifically, analogue image information of a subject is first generated using a solid-state image sensing device such as a CCD (charge-coupled device) or CMOS sensor. The analogue image information is converted into digital image data by an analogue front end, and then the converted image data is stored in a buffer memory under the control of an image processing controller.
Then, the image processing controller reads out image data from the buffer memory, and stores again the imaged data in the buffer memory after performing processing such as white balance correction. Subsequently, the image data is read out again frame-by-frame from the buffer memory under control of the image processing controller, and converted into a video signal. The video signal is transferred to a view finder of an LCD display device and displayed thereon after resized into a predetermined size for display on the view finder.
Such a buffer memory is used as memory for a temporal storage of data such as image data, and is used as a work area in executing various processing on the image data.
Also in a digital still camera, an LCD monitor is generally used for checking an image after imaging or picking up. According to the configuration as disclosed in Patent Document 1, in display on the LCD monitor, an image processing controller again reads out image data stored in the buffer memory and stores the read out image data in the buffer memory after executing predetermined imaging processing such as white balance correction, tone correction, color correction and the like. The image data stored in the buffer memory is again read out and converted into a video signal, and outputted to an LCD monitor for display after being resized into a predetermined size suitable for display on the LCD monitor.
Although not being the case of a camera module, Japanese Patent Laying-Open No. 2000-023108 (Patent Document 2) and Japanese Patent Laying-Open No. 2001-125548 (Patent document 3) disclose the use of a scan converter as an interface for matching the synchronization frequencies of an input image display format and an output image display format when these formats are different from each other.
In the configuration shown in Japanese Patent Document 2, line memories for storing several lines of pixel data are used as a buffer memory for storing image data. In this case, controls of input and output are not performed on a frame basis. In the case of such writing/reading, different clock signals are used for a writing clock signal and a reading clock signal. When a phase lag between a horizontal synchronization signal and the writing clock signal on an input side differs from a phase lag between a horizontal synchronization signal and a reading clock signal on an output side, jitter occurs in a displayed image on the output side. In Patent Document 2, for preventing such jitter, writing of a line memory is performed as follows. On the input side, pixel data is written into the line memory after amplitude correction depending on a time difference (phase difference) between the horizontal synchronization signal and the writing clock signal. In this amplitude correction, a differential value in amplitude between adjacent input pixels is divided by a cycle time of the writing clock signal. Thereafter, it is multiplied by time difference between the writing clock signal and the writing horizontal synchronization signal, to generate writing pixel data.
In the configuration shown in Patent Document 3, similarly, a line memory is used for a buffer memory for pixel data storage. In Patent Document 3, when the line memory is used for a buffer memory, different clock signals are used doe a writing clock signal and for a reading clock signal. In order to adjust the difference in timing between the writing and reading clock signals, timing is adjusted in writing and reading of pixel data. Specifically, the periods of the input-side and output-side horizontal synchronization signals are adjusted in units of one operation clock signal period in accordance with difference in resolution between the input side and the output side. In the adjustment of the cycle periods of the horizontal synchronization signals, the number of horizontal synchronization signals in one vertical scanning period is adjusted. When writing into and reading from the line memories are started concurrently from the same initial position, overflow/underflow may occur in the line memories due to difference between writing rate and reading rate. In Patent Document 3, reading start position of the line memories is calculated and set initially in order to prevent such underflow or overflow.
In the configuration of a digital camera shown in Patent Document 1, a memory that stores several frames of image data is used as a buffer memory. Therefore, the buffer memory is large in storage capacity, and is difficult to integrate on one chip together with an image processing controller for a one-chip system LSI. This is an obstacle to down-sizing/up-integration. When a frame memory is connected outside the image processing controller, it is necessary to make circuits, such as external bus controller and a DMA (direct memory access) controller for conducting input/output of image data, operate. The DMA controller is provided for directly performing writing/reading of image data not through a CPU serving as a main controller. For this reason, the problem of increased power dissipation arises. When the frame memory is provided externally, operation clock frequency of circuit such as external bus controller and DMA controller can be reduced only to such a clock rate at which data can be written into and read from the frame memory without any delay. This disadvantageously makes it difficult to reduce the power consumption during use of the view finder.
In Patent Document 2, amplitude of input pixel data is corrected, in accordance with time difference between the input horizontal synchronization signal and the writing clock signal, in writing image data into the line memories. This correction of amplitude is based on the assumption that amplitude of pixel data changes linearly between adjacent pixels. When the image changes gently, the correction of amplitude may be made according to this linearly proportional distribution. However, in the area where the image rapidly changes such as at the contour, there is a possibility that the corrected pixel data may not correspond to the input pixel data. This leads the problem of difficulty of accurately reproducing an image.
Also, in Patent Document 2, writing and reading of pixel data to/from the line memories are performed in synchronization with separate operation clock signals. Phase/frequency lag between these operation clock signals may cause overflow/underflow in the line memories. However, Patent Document 2 does not consider such situation.
Patent Document 3 considers the problem of synchronization of writing and reading of image data in scan conversion using the line memories. However, in Patent Document 3, in an initialization sequence, horizontal scanning period on the output side is adjusted in accordance with difference in resolution between input side and output side, to adjust the number of horizontal scanning lines displayed on the screen in a valid display region is set to the value suited to the display resolution. It is determined whether a product of the adjusted display pixel number and a period of the clock signal on the input side is equal to a product of the display pixel number and the period of the output clock signal on the output side. In an operation of adjusting the period of the horizontal synchronization signal, horizontal scanning period is increased or decreased by one cycle period of operation clock signal according to each determination result. Finally, whether the number of horizontal scanning lines in the valid image region has reached an intended value is determined. The adjustment of horizontal scanning period is executed repeatedly until the intended number of horizontal scanning lines is displayable. Therefore, complicated calculation should be made so as to establish the horizontal synchronization, and a long time is required for making such determination. Further, the cycle period of the output horizontal synchronization signal is adjusted in units of operation clock signals, so that this initialization sequence is time-consuming. As a result, in a digital still camera, time is consumed until an image to be imaged is accurately displayed in the view finder and the perfect shot may possibly be missed when the procedure of establishing synchronization as shown in Patent Document 3 is employed.
In Patent Document 3, once reading timing of pixel data on the output side is established in the initialization sequence, subsequent reading of pixel data from the line memories is fixedly executed at this established timing. Therefore, when the frequency of the operation clock signal varies, for example, due to variation in power supply voltage during operation state, accurate reading and reproduction of image data may not be allowed.
Therefore, the configurations of the scan converters shown in Patent Documents 2 and 3 are difficult to be directly applied to the configuration of displaying on a view finder or LCD monitor of e.g., a digital still camera or a digital video camera.